Host Bus Adapters (HBAs) connected to Periphery Component Interconnect Express (PCIe) interfaces may be used to drive a variety of peripheral devices, such as RAID On Chip (ROC) backup memory systems. Many PCIe based HBA solutions, such as a ROC HBA, provide a battery backed DRAM, typically a DDR3 memory chip, on the HBA board. Battery back-up DRAM is an option to retain the contents of the memory when there is an unexpected power loss, which is an important feature of an ROC based HBA. In order to increase performance, reduce device failure vulnerability, and provide redundant paths, many PCIe based HBAs may be included in a single server.
ROC applications typically include three or more ROCs implemented on separate HBAs. Currently, each PCIe connected ROC in a multiple ROC system requires a separate DDR3 memory with its own dedicated battery located on each HBA board. This results in replication of the battery and the DRAM memory on each HBA board. The functionality of each battery and DRAM is the same and the replication of these components over multiple HBAs adds considerable cost and complexity to the system. There is, therefore, a continuing need for improved HBA technology for PCIe implementations.